1. Field of the Invention
This invention generally relates to semiconductors and fabrication methods therefor and, more particularly, to a semiconductor device having an Oxide Nitride Oxide (ONO) film and a fabrication method for the same.
2. Description of the Related Art
In recent years, non-volatile memory semiconductor devices, in which data is rewritable, have been widely used. In the technical field of such non-volatile memories, developments downsizing the memory cells are being promoted to obtain higher storage capacity.
As non-volatile memories, floating-gate flash memories, in which the charge is stored in a floating gate, have been widely used. However, when the memory cell is downsized to realize high memory density in recent years, the internal voltage must necessarily be lowered, resulting in a requirement to reduce the thickness of the tunnel oxide film thereof. However, reducing the thickness of the tunnel oxide film increases the leakage current flowing across such film. In addition, defects introduced into the tunnel oxide film cause a problem in reliability that results in loss of the charge stored in the floating gate.
To address this problem, there have been developed flash memories having an Oxide/Nitride/Oxide (ONO) film such as a Metal Oxide Nitride Oxide Silicon (MONOS) or Silicon Oxide Nitride Oxide Silicon (SONOS). These are a type of flash memory in which the charge is stored in silicon nitride film, also known as a trapping layer, interposed between two silicon oxide films. In this type of flash memory, the charge is stored in the silicon nitride film which serves as an insulating film. Therefore, even if there is a defect in the tunnel oxide film, charge loss is minimized, unlike floating-gate type flash memories. A flash memory having an ONO film is described in, for example, Boaz Eitan et al., Electron Device Letters, Vol. 21, No. 11, pp. 543-545(2000) (hereinafter referred to as Non-Patent Document 1).
A description will next be given, with reference to FIG. 1 through FIG. 4, of a flash memory having a conventional ONO film and the fabrication method thereof (hereinafter, referred to as a conventional technique). The flash memory includes a memory cell region and a peripheral circuit region. FIG. 1 is a top view of the memory cell region in accordance with the conventional technique (a protection film 32, an interlayer insulating film 30, an interconnection 34, and an ONO film 16 are not shown), and FIG. 2 is an enlarged view of FIG. 1. FIG. 3 is a cross-sectional view taken along a line A-A′ shown in FIG. 2. FIG. 4 is a cross-sectional view taken along a line B-B′ shown in FIG. 2. A bit line 14 is provided in a given region of a P-type silicon semiconductor substrate 10. As the ONO film 16, there are provided a silicon oxide film serving as the tunnel oxide film, a silicon nitride film serving as the trapping layer, and another silicon oxide film serving as the top oxide film, on the semiconductor substrate 10. A polysilicon film is formed in a given region on the ONO film 16 as a word line 20 to be a gate of a core cell.
In a bit line connecting region 42, the bit line 14 and the interconnection 34 are connected via a contact hole 40 provided in the interlayer insulating film 30. One bit line connecting region 42 is provided at intervals of multiple word lines 20. To downsize the memory cell, the distance between the bit lines must be narrowed and the distance between the word lines, including the bit line connecting region 42, must also be narrowed.
The conventional technique, however, has a problem in that the distance between the bit lines are hard to downsize because the overlapping margin of the bit line 14 and the contact hole 40 has to be ensured during exposure. Referring now to FIG. 5, a description will be given of a related problem caused by a misaligned overlapping of the bit line 14 and the contact hole 40 during exposure in a direction vertical to the bit line 14. FIG. 5 is a view showing a case where the contact hole 40 is not aligned with the bit line 14 in a left-hand direction. In a region represented by a reference numeral 55, the contact hole 40 is in touch with the P-type silicon semiconductor substrate 10. This contact in the region 55 allows leakage current to flow between the bit line 14 and the semiconductor substrate 10 via the contact hole 40. To prevent this leakage, an overlapping margin of the bit line 14 and the contact hole 40 during exposure is assured and then the width of the bit line 14 and the distance between the bit lines 14 are determined. Yet, assuring the overlapping margin makes it difficult to decrease the distance between the bit lines 14.